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| M80C186EB-16 -13 -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Full Static Operation True CMOS Inputs and Outputs b55 C to a 125 C Operating Temperature Range Y Integrated Feature Set Low-Power Static CPU Core Two Independent UARTs each with an Integral Baud Rate Generator Two 8-Bit Multiplexed I O Ports Programmable Interrupt Controller Three Programmable 16-Bit Timer Counters Clock Generator Ten Programmable Chip Selects with Integral Wait-State Generator Memory Refresh Control Unit System Level Testing Support (ONCE Mode) Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O Speed Versions Available 16 MHz (M80C186EB-16) 13 MHz (M80C186EB-13) 8 MHz (M80C186EB-8) Y Low-Power Operating Modes Idle Mode Freezes CPU Clocks but keeps Peripherals Active Powerdown Mode Freezes All Internal Clocks Complete System Development Support ASM86 Assembler PL M 86 Pascal 86 Fortran 86 C-86 and System Utilities In-Circuit Emulator (ICE TM -186EB) Supports M80C187 Numeric Coprocessor Interface Available In 88-Lead Pin Grid Array (MG80C186EB) Y Y Y Y Y The M80C186EB is a second generation CHMOS High-Integration microprocessor It has features that are new to the M80C186 family and include a STATIC CPU core an enhanced Chip Select decode unit two independent Serial Channels I O ports and the capability of Idle or Powerdown low power modes 271214 - 1 April 1990 Order Number 271214-002 M80C186EB-16 -13 -8 16-Bit High-Integration Embedded Processor CONTENTS INTRODUCTION OVERVIEW M80C186EB Core Architecture Register Set Instruction Set Memory Organization Addressing Modes Data Types Interrupts Bus Interface Unit Clock Generator M80C186EB Peripheral Architecture Interrupt Control Unit Timer Counter Unit Serial Communications Unit Chip-Select Unit I O Port Unit Refresh Control Unit Power Management Unit M80C187 Interface ONCE Test Mode PACKAGE INFORMATION Pin Descriptions M80C186EB PINOUT ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings OPERATING CONDITIONS RECOMMENDED CONNECTIONS DC SPECIFICATIONS ICC versus Frequency and Voltage PDTMR Pin Delay Calculation PAGE 4 4 4 4 5 5 5 7 7 9 9 10 10 10 12 12 13 13 13 13 13 14 14 19 21 21 21 21 22 23 23 CONTENTS AC SPECIFICATIONS AC Characteristics M80C186EB-16 AC Characteristics M80C186EB-13 AC Characteristics M80C186EB-8 Relative Timings (M80C186EB-16 -13 -8) Serial Port Mode 0 Timings (M80C186EB-16 -13 -8) AC TEST CONDITIONS AC TIMING WAVEFORMS DERATING CURVES RESET COLD RESET WAVEFORMS WARM RESET WAVEFORMS BUS CYCLE WAVEFORMS REGISTER BIT SUMMARY M80C186EB EXECUTION TIMINGS INSTRUCTION SET SUMMARY FOOTNOTES 88-LEAD CERAMIC PIN GRID ARRAY PACKAGE ERRATA REVISION HISTORY PAGE 24 24 25 26 27 28 29 29 32 33 34 35 36 44 48 49 54 55 56 56 2 M80C186EB 271214 - 2 Figure 1 M80C186EB Block Diagram 3 M80C186EB INTRODUCTION The M80C186EB is the first product in a new generation of low-power high-integration microprocessors It enhances the existing 186 family by offering new features and new operating modes The M80C186EB is object code compatible with the M80C186 M80C188 microprocessors The feature set of the M80C186EB meets the needs of low power space critical applications Low-Power applications benefit from the static design of the CPU core and the integrated peripherals Minimum current consumption is achieved by providing a Powerdown mode that halts operation of the device and freezes the clock circuits Peripheral design enhancements ensure that non-initialized peripherals consume little current Space critical applications benefit from the integration of commonly used system peripherals Two serial channels are provided for services such as diagnostics inter-processor communication modem interface terminal display interface and many others A flexible chip select unit simplifies memory and peripheral interfacing The interrupt unit provides sources for up to 129 external interrupts and will prioritize these interrupts with those generated from the on-chip peripherals Three general purpose timer counters and sixteen multiplexed I O port pins round out the feature set of the M80C186EB M80C186EB Core Architecture REGISTER SET The M8086 M8088 M80186 M80C186 and M80C188 all contain the same basic set of registers instructions and addressing modes The M80C186EB is upward compatible with all of these microprocessors The M80C186EB base architecture has fourteen 16-bit registers as shown in Figure 2 There are eight general purpose registers which may be used for arithmetic and logic operands Four of these registers (AX BX CX and DX) can be used as 16-bit registers or split into pairs of separate 8-bit registers The other four registers (BP SI DI and SP) may also be used to determine offset addresses of operands in memory These registers may contain base addresses or indexes to particular locations within a segment The addressing mode selects the specific registers for operand and address calculations Another four 16-bit registers (CS DS ES SS) select the segments of memory that are immediately addressable for code stack and data There are two remaining special purpose registers (IP and F) that record or alter certain aspects of the M80C186EB processor state 15 AH AL BL CL DL 0 AX BX CX DX SI DI BP SP OVERVIEW Figure 1 shows a block diagram of the M80C186EB The Execution Unit (EU) is an enhanced M8086 CPU core that includes dedicated hardware to speed up effective address calculations enhance execution speed for multiple-bit shift and rotate instructions and for multiply and divide instructions string move instructions that operate at full bus bandwidth ten new instruction and full static operation The Bus Interface Unit (BIU) is the same as that found on the original 186 family products except the queue-status mode has been deleted and buffer interface control has been changed to ease system design timings An independent internal bus is used to allow communication between the BIU and internal peripherals BH CH DH Source Index Destination Index Base Pointer Stack Pointer Code Segment Stack Segment Data Segment Extra Segment CS SS DS ES Instruction Pointer Flags IP F Figure 2 M80C186EB Register Set 4 M80C186EB INSTRUCTION SET The instruction set is divided into seven categories data transfer arithmetic shift rotate logical string manipulation control transfer high-level instructions and processor control These categories are summarized in Figure 4 An M80C186EB instruction can reference anywhere from zero to several operands An operand can reside in a register in the instruction itself or in memory MEMORY ORGANIZATION Memory is organized in sets of segments Each segment is a linear contiguous sequence of up to 64K (216) 8-bit bytes Memory is addressed using a twocomponent address (a pointer) that consists of a 16-bit base segment and a 16-bit offset The 16-bit base segment values are contained in one of four internal segment registers (code data stack extra) The physical address is calculated by shifting the base value left by four bits and adding the 16-bit offset value to yield a 20-bit physical address (see Figure 3) The resulting 20-bit address allows for a 1 Mbyte address range Table 1 Segment Register Selection Rules Memory Segment Reference Register Needed Used Implicit Segment Selection Rule Instructions Code (CS) Instruction prefetch and immediate data Stack Stack (SS) All stack pushes and pops any memory references which use the BP register as a base Extra (ES) All String instruction references which use the DI register as an index External Local Data Data (DS) All other data references ADDRESSING MODES The M80C186EB provides eight categories of addressing modes to specify operands Two addressing modes are provided for instructions that operate on register or immediate operands Register Operand Mode The operand is located in one of the 8- or 16-bit general registers Immediate Operand Mode The operand is included in the instruction Six modes are provided to specify the location of an operand in a memory segment A memory operand address consists of two 16-bit components a segment base and an offset The segment base is supplied by a 16-bit segment register either implicitly chosen by the addressing mode or explicitly chosen by a segment override prefix The offset also called the effective address is calculated by summing any combination of the following three address elements 271214 -3 the displacement (an 8- or 16-bit immediate value contained in the instruction) Figure 3 Two Component Address All instructions that address operands in memory must specify the base segment and the 16-bit offset value For speed and compact instruction encoding the segment register used for a physical address generation is implied by the addressing mode used (see Table 1) Special segment override instruction prefixes allow the implicit segment register selection rules to be overridden for special cases The code stack data and extra segments may coincide for simple programs the base (contents of either the BX or BP base registers) and the index (contents of either the SI or DI index registers) 5 M80C186EB GENERAL PURPOSE MOV PUSH POP PUSHA POPA XCHG XLAT INPUT OUTPUT IN OUT ADDRESS OBJECT LEA LDS LES FLAG TRANSFER LAHF SAHF PUSHF POPF ADDITION DIVISION DIV IDIV AAD CBW CWD STRING OPERATIONS MOVS INS OUTS CMPS SCAS LODS STOS REP REPE REPZ REPNE REPNZ LOGICALS NOT AND OR XOR TEST SHIFTS NO OPERATION NOP HIGH LEVEL INSTRUCTIONS ENTER LEAVE BOUND CONDITIONAL TRANSFERS JA JNBE JAE JNB JB JNAE JBE JNA JC JE JZ JG JNLE JGE JNL JL JNGE JLE JNG JNC JNE JNZ JNO JNP JP0 JNS JO JP JPE JS UNCONDITIONAL TRANSFERS CALL RET JMP ITERATION CONTROLS LOOP LOOPE LOOPZ LOOPNE LOOPNZ JCXZ INTERRUPTS INT INTO IRET ADD INC AAA DAA SUBSTRACTION SUB SBB DEC NEG CMP AAS DAS MULTIPLICATION MUL IMUL AAM SHL SAL SHR SAR ROTATES ROL ROR RCL RCR FLAG OPERATIONS STC CLC CMC STD CLD STI CLI EXTERNAL SYNCHRONIZATION HLT WAIT LOCK Figure 4 M80C186EB Instruction Set 6 M80C186EB Any carry out from the 16-bit addition is ignored 8-bit displacements are sign extended to 16-bit values Combinations of these three address elements define the six memory addressing modes described below Packed BCD A byte (packed) representation of two decimal digits (0 - 9) One digit is stored in each nibble (4 bits) of the byte Floating Point A signed 32- 64- or 80-bit real number representation Floating point operands are supported when using the M80C187 Numeric Coprocessor In general individual data elements must fit within defined segment limits INTERRUPTS An interrupt transfers execution to a new program location The old program address (CS IP) and machine state (F) are saved on the stack to allow resumption of the interrupted program Interrupts fall into three classes hardware initiated software (program) initiated and instruction exception initiated Hardware initiated interrupts occur in response to an external or internal input and are classified as nonmaskable or maskable Programs may cause an interrupt by executing the ``INT'' instruction Instruction exceptions occur when an illegal opcode has been fetched into the queue and is read by the execution unit Another type of exception can be generated when executing an ``ESC'' instruction For all cases except the ``ESC'' exception the return address from an exception will point at the instruction immediately following the instruction causing the exception The return address after an ``ESC'' exception will point back to the ESC instruction causing the exception or to the segment override prefix immediately preceding the ESC instruction if the prefix was present A table containing up to 256 pointers defines the proper interrupt service routine for each interrupt Interrupts 0 - 31 are reserved by Intel Table 2 shows the M80C186EB predefined type and default priority levels For each interrupt an 8-bit vector (Vector Type) identifies the appropriate table entry Multiplying the 8-bit vector by 4 defines the vector address INT instructions contain or imply the vector type and allow access to all 256 interrupts Direct Mode The operand's offset is contained in the instruction as an 8- or 16-bit displacement element Register Indirect Mode The operand's offset is in one of the registers SI DI BX or BP Based Mode The operand's offset is the sum of an 8- or 16-bit displacement and the contents of a base register (BX or BP) Indexed Mode The operand's offset is the sum of an 8- or 16-bit displacement and the contents of an index register (SI or DI) Based Indexed Mode The operand's offset is the sum of the contents of a base register and an index register Based Indexed Mode with Displacement The operand's offset is the sum of a base register's contents an index register's contents and an 8- or 16-bit displacement DATA TYPES The M80C186EB directly supports the following data types Integer A signed binary numeric value contained in an 8-bit byte or 16-bit word All operations assume a 2's complement representation Signed 32- and 64-bit integers are supported using the M80C187 Numerics Coprocessor Ordinal An unsigned binary numeric value contained in an 8-bit byte or 16-bit word Pointer A 16- or 32-bit quantity composed of a 16-bit offset component or a 16-bit segment base component and a 16-bit offset component String A contiguous sequence of bytes or words A string may contain from 1 Kbyte to 64 Kbytes ASCII A byte representation of alphanumeric and control characters using the ASCII standard of character representation BCD A byte (unpacked) representation of the decimal digits 0- 9 7 M80C186EB Table 2 M80C186EB Interrupt Vectors Interrupt Name Divide Error Single Step Interrupt Non-Maskable Interrupt One Byte Interrupt Interrupt on Overflow Array Bounds Check Invalid OP-Code ESC OP-Code Interrupt Timer 0 Interrupt Reserved INT0 Interrupt INT1 Interrupt INT2 Interrupt INT3 Interrupt Numerics Exception INT4 Interrupt Timer1 Interrupt Timer2 Interrupt UART 0 Receive Interrupt UART 0 Transmit Interrupt Reserved Vector Type 0 1 2 3 4 5 6 7 8 9-11 12 13 14 15 16 17 18 19 20 21 22-31 Vector Address 00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H - 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H - 7CH 5 6 7 8 1 4 2A 2B 3 3A ESC OP-Codes Default Priority 1 1A 1 1 1 1 1 1 2 Related Instructions DIV IDIV All INT 2 or NMI INT INT0 BOUND Illegal Inst ESC OP-Codes 8 M80C186EB BUS INTERFACE UNIT The M80C186EB core incorporates a bus controller that generates local bus control signals In addition it employs a HOLD HLDA protocol to share the local bus with other bus masters The bus controller is responsible for generating 20 bits of address read and write strobes bus cycle status information and data (for write operations) information It is also responsible for reading data off the local bus during a read operation A READY input pin is provided to extend a bus cycle beyond the minimum four states (clocks) A HOLD HLDA protocol is provided by the local bus controller to allow multiple bus masters to share the same local bus When the M80C186EB relinquishes control of the local bus it floats certain bus control signals to allow another bus master to drive these pins directly Refer to the Pin Description section to determine which pins the M80C186EB will float during a HOLD HLDA bus exchange The M80C186EB local bus controller also generates two control signals (DEN and DT R) when interfacing to external transceiver chips This capability allows the addition of transceivers for simple buffering of the mulitplexed address data bus CLOCK GENERATOR The M80C186EB provides an on-chip clock generator for both internal and external clock generation The clock generator features a crystal oscillator a divide-by-two counter and two low-power operating modes The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-overtone mode crystal network Alternatively the oscillator circuit may be driven from an external clock source Figure 5 shows the various operating modes of the M80C186EB oscillator circuit The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter This counter is used to drive all internal phase clocks and the external CLKOUT signal CLKOUT is a 50% duty cycle processor clock and can be used to drive other system components All AC timings are referenced to CLKOUT The following parameters are recommended when choosing a crystal Temperature Range Application Specific ESR (Equivalent Series Resistance) 40X max C0 (Shunt Capacitance of Crystal) 7 0 pF max CL (Load Capacitance) 20 pF g 2 pF Drive Level 1 mW max 271214 - 5 271214 -4 (A) Crystal Connection NOTE The L1C1 network is only required when using a thirdovertone crystal (B) Clock Connection Figure 5 M80C186EB Clock Configurations 9 M80C186EB Internal interrupt sources include the Timers and Serial channel 0 External interrupt sources come from the five input pins INT4 0 The NMI interrupt pin is not controlled by the ICU and is passed directly to the CPU Although the Timer and Serial channel each have only one request input to the ICU separate vector types are generated to service individual interrupts within the Timer and Serial channel units The M80C186EB ICU provides a mechanism for expanding the number of external interrupt sources Two pairs of pins can be independently configured to support an external slave interrupt controller (82C59A) Each pair of external pins can be expanded to support 64 interrupts making it possible for the M80C186EB to support a total of 129 external interrupts The ICU may be used in a polled mode if interrupts are undesirable When polling the processor disables interrupts and then polls the ICU whenever it is convenient TIMER COUNTER UNIT The M80C186EB Timer Counter Unit (TCU) provides three 16-bit programmable timers Two of these are highly flexible and are connected to external pins for control or clocking A third timer is not connected to any external pins and can only be clocked internally However it can be used to clock the other two timer channels The TCU can be used to count external events time external events generate non-repetitive waveforms generate timed interrupts etc Each timer has at least one 16-bit compare register and one 16-bit count register Timers 0 and 1 each have an additional 16-bit compare register The count register is incremented every fourth CPU clock cycle (internal clocking) every time Timer2 expires (Timers 0 and 1 only) or every Low-to-High transition on the timer input pin (Timers 0 and 1 only) The input clock to Timers 0 and 1 must not exceed one fourth the operating frequency of the M80C186EB When the count register matches the value programmed into the compare register several operations may happen All three timers can generate an interrupt when the compare register matches the value in the count register Additionally Timers 0 and 1 have an output pin that can change state or pulse when the compare condition occurs M80C186EB Peripheral Architecture The M80C186EB has integrated several common system peripherals with a CPU core to create a compact yet powerful system The integrated peripherals are designed to be flexible and provide logical interconnections between supporting units (e g the interrupt control unit supports interrupt requests from the timer counters or serial channels) The list of integrated peripherals include 7-Input Interrupt Control Unit 3-Channel Timer Counter Unit 2-Channel Serial Communications Unit 10-Output Chip-Select Unit I O Port Unit Refresh Control Unit Power Management Unit The registers associated with each integrated periheral are contained within a 128 x 16 register file called the Peripheral Control Block (PCB) The PCB can be located in either memory or I O space on any 256 Byte address boundary During bus cycles that access the PCB the bus controller will signal the operation externally (i e the RD WR status address data etc lines will be driven as in a normal bus cycle) However READY is ignored and the contents of the data bus during a read operation is ignored The starting address of the PCB is controlled by a relocation register and can overlap any of the memory or I O regions programmed into the Chip Select Unit In this case the overlapped chip select will not go active when the PCB is read or written Figure 6 provides a list of the registers associated with the PCB The Register Bit Summary at the end of this specification individually lists all of the registers and identifies each of their programming attributes INTERRUPT CONTROL UNIT The M80C186EB can receive interrupts from a number of sources both internal and external The interrupt control unit serves to merge these requests on a priority basis for individual service by the CPU Each interrupt source can be independently masked by the Interrupt Control Unit (ICU) or all interrupts can be globally masked by the CPU 10 M80C186EB PCB Offset 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH 1CH 1EH 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H Function Reserved End Of Interrupt Poll Poll Status Interrupt Mask Priority Mask In-Service Interrupt Request Interrupt Status Timer Control Serial Control INT4 Control INT0 Control INT1 Control INT2 Control INT3 Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Timer0 Count PCB Offset 40H 42H 44H 46H 48H 4AH 4CH 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H 7AH 7CH 7EH Function Timer2 Count Timer2 Compare Reserved Timer2 Control Reserved Reserved Reserved Reserved Reserved Port0 Pin Port0 Control Port0 Latch Port1 Direction Port1 Pin Port1 Control Port1 Latch Serial0 Baud Serial0 Count Serial0 Control Serial0 Status Serial0 RBUF Serial0 TBUF Reserved Reserved Serial1 Baud Serial1 Count Serial1 Control Serial1 Status Serial1 RBUF Serial1 TBUF Reserved Reserved PCB Offset 80H 82H 84H 86H 88H 8AH 8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH A0H A2H A4H A6H A8H AAH ACH AEH B0H B2H B4H B6H B8H BAH BCH BEH Function GCS0 Start GCS0 Stop GCS1 Start GCS1 Stop GCS2 Start GCS2 Stop GCS3 Start GCS3 Stop GCS4 Start GCS4 Stop GCS5 Start GCS5 Stop GCS6 Start GCS6 Stop GCS7 Start GCS7 Stop LCS Start LCS Stop UCS Start UCS Stop Relocation Reserved Reserved Reserved Refresh Base Refresh Time Refresh Control Refresh Address Power Control Reserved Step ID Reserved PCB Offset C0H C2H C4H C6H C8H CAH CCH CEH D0H D2H D4H D6H D8H DAH DCH DEH E0H E2H E4H E6H E8H EAH ECH EEH F0H F2H F4H F6H F8H FAH FCH FEH Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 32H Timer0 Compare A 34H Timer0 Compare B 36H 38H Timer0 Control Timer1 Count 3AH Timer1 Compare A 3CH Timer1 Compare B 3EH Timer1 Control Figure 6 M80C186EB Peripheral Control Block Registers 11 M80C186EB Other timer programming options include Additional features of the SCU include Framing error receive buffer overrun error and parity error detection All three timers can be set to halt or continue after a compare match Timers 0 and 1 can be reset or retriggered using their respective input pins Break detect Break send CHIP-SELECT UNIT TCU registers can be read or written at any time SERIAL COMMUNICATIONS UNIT The Serial Control Unit (SCU) of the M80C186EB contains two independent channels Each channel is identical in operation except that only channel 0 is supported by the integrated interrupt controller (channel 1 has an external interrupt pin) Each channel has its own baud rate generator that is independent of the Timer Counter Unit and can be internally or externally clocked at up to one half the M80C186EB operating frequency Each serial channel supports one synchronous and four asynchronous modes of operation and is compatible with the serial ports of the MCS -51 and MCS -96 family of products Data field length can be 7- 8- or 9-bits with optional odd or even parity (generated and checked) and one stop bit (generated and checked) The 9-bit mode has an optional ``addressing'' feature to simplify interprocessor communication Each serial port is doubled buffered in both transmit and receive operation (data can be read or written to a buffer register while data is shifted into or out of a shifting register respectively) A Clear-To-Send input pin can be programmed to prevent data transmission if the pin is sampled inactive Serial channel 0 is supported by the integrated interrupt controller providing separate receive and transmit vector types Serial channel 1 has an external interrupt pin which OR's the receive and transmit interrupts This external interrupt pin can be routed to either the external pins of the ICU the NMI pin or any other external system interrupt controller Status bits are provided to allow polling of the serial channels if interrupts are not desired Independent baud rate generators are provided for each of the serial channels For the asynchronous modes the generator supplies an 8x baud clock to both the receive and transmit register logic A 1x baud clock is provided in the synchronous mode The M80C186EB Chip-Select Unit (CSU) integrates logic which provides up to ten programmable chipselects to access both memories and peripherals In addition each chip-select can be programmed to automatically insert additional clocks (wait-states) into the current bus cycle and automatically terminate a bus cycle independent of the condition of the READY input pin Each of the chip-selects can be programmed to go active for either memory or I O accesses UCS is the only chip-select that is active after a reset and is enabled for memory addresses in the range 0FFC00H to 0FFFFFH (this allows a boot-ROM to be accessed using UCS) Every chip-select has a programmable start and stop register that defines the active region for the chip-select and the ready characteristics for the region The start and stop address fields are 10 bits in length and are matched against the upper 10 bits of either the memory or I O address A 10-bit compare results in a granularity of 1 Kbytes for memory accesses and 64 bytes for I O accesses Each chip select can be disabled by programming its start address greater than its stop address or by clearing its enable bit Each chip-select can be programmed to automatically insert wait-states and to control whether the external READY input is to be ignored or used The M80C186EB bus controller will wait the programmed number of wait-states before the external READY pin can be used to extend or terminate the bus cycle Overlapping of chip-selects is allowed However each one that overlaps will go active If any overlapping chip-select has been programmed to use external ready the bus control unit will insert the least amount of programmed wait-states programmed before the external ready pin is used If all overlapped chip-selects ignore external ready the bus controller will insert the maximum number of programmed wait-states Any chip-select that overlaps the Peripheral Control Block (PCB) will not go active for that portion of the address range allocated to the PCB 12 M80C186EB The Generic Chip-Selects (GCS7 0) are multiplexed with an output only Port function Any channel that is being used as a chip-select must be disabled as a port pin by correctly programming the port pin control registers (see the following section) I O PORT UNIT The I O Port Unit (IPU) on the M80C186EB supports two 8-bit channels of input output or input output operation Port 1 is multiplexed with the chip select pins and is output only Most of Port 2 is multiplexed with the serial channel pins Port 2 pins are limited to either an output or input function depending on the operation of the serial pin it is multiplexed with Two bits of Port 2 are not multiplexed with any other peripheral functions and can be used as either an input or an output function A port direction register is used to define the function of the port pin The output for these two pins are open drain Besides a direction register each port channel has a data latch register port pin register and a port multiplexer control register REFRESH CONTROL UNIT The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed A 9-bit counter controls the number of clocks between refresh requests A 12-bit address generator is maintained by the RCU and is presented on the A12 1 address lines during the refresh bus cycle The address generator is incremented only after the refresh bus cycle is run This ensures that all address combinations will be presented to the memory array even if the refresh bus cycle is not run before another request is generated Address bits A19 13 are programmable to allow the refresh address block to be located on any 8 Kbyte boundary The chip-select unit is active during refresh bus cycles This means that a chip-select will go active if the refresh address is within the limits specified for the channel In addition BHE and A0 are both driven high during refresh bus cycles (this is normally an invalid bus condition) Data on the AD15 0 bus is ignored POWER MANAGEMENT UNIT The M80C186EB Power Management Unit (PMU) is provided to control the power consumption of the device The PMU provides three power modes Active Idle and Powerdown Active Mode indicates that all units on the M80C186EB are functional and the device consumes maximum power (depending on the level of peripheral operation) Idle Mode freezes the clocks of the Execution and Bus units at a logic zero state (all peripherals continue to operate normally) An unmasked interrupt NMI or reset will cause the M80C186EB to exit the Idle mode The Powerdown mode freezes all internal clocks at a logic zero level and disables the crystal oscillator All internal registers hold their values provided VCC is maintained Current consumption is reduced to just transistor junction leakage An NMI or processor reset will cause the M80C186EB to exit the Powerdown Mode A timing pin is provided to establish the length of time between exiting Powerdown and resuming device operation (Length of time depends on startup time of crystal oscillator and is application dependent ) A pending refresh request will attempt to abort a HOLD HLDA bus exchange HLDA is deasserted when a refresh request is pending and a bus HOLD is already in progress HOLD must then be released in order for the M80C186EB to execute the refresh bus cycle M80C187 Interface The M80C186EB supports the direct connection of the M80C187 Numerics Coprocessor ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system the M80C186EB has a test mode available which forces all output and input output pins to be placed in the high-impedance state ONCE stands for ``ON Circuit Emulation'' The ONCE mode is selected by forcing the A19 ONCE pin LOW (0) during a processor reset (this pin is weakly held to a HIGH (1) level) while RESIN is active 13 M80C186EB PACKAGE INFORMATION This section describes the pins pinouts and thermal characteristics for the M80C186EB PGA package For complete package specifications and information see the Intel Packaging Outlines and Dimensions Guide (Order Number 231369) I O Table 3 Pin Description Nomenclature Symbol Input Only Pin Output Only Pin Pin can be either input or output Pin ``must be'' connected as described Description IO Pin Descriptions The M80C186EB pins are described in this section Table 3 presents the legend for interpreting the pin descriptions in Table 4 Figure 7 provides an example pin description entry The ``I O'' signifies that the pins are bidirectional (i e have both an input and output function) The ``S'' indicates that as an input the signal is synchronized to CLKOUT for proper operation The ``H(Z)'' indicates that these pins will float while the processor is in the Hold Acknowledge state R(Z) indicates that these pins will float while RESIN is low P(X) Indicates that these pins will retain its current value when Idle or Powerdown Modes are entered All pins float while the processor is in the ONCE Mode except OSCOUT (OSCOUT is required for crystal operation) Name Type AD15 0 IO S(L) H(Z) R(Z) P(X) Description These pins provide a multiplexed ADDRESS and DATA bus During the address phase of the bus cycle address bits 0 through 15 are presented on the bus and can be latched using ALE 8- or 16-bit data information are transferred during the data phase of the bus cycle S( ) Synchronous Input must meet setup and hold times for proper operation of the processor The pin is S(E) edge sensitive S(L) level sensitive Asynchronous Input must meet setup and hold only to guarantee recognition The pin is A(E) edge sensitive A(L) level sensitive While the processor's bus is in the Hold Acknowledge state the pin H(1) is driven to VCC H(0) is driven to VSS H(Z) floats H(Q) remains active H(X) retains current state While the processor's RES line is low the pin R(1) is driven to VCC R(0) is driven to VSS R(Z) floats R(WH) weak pullup R(WL) weak pulldown While Idle or Powerdown modes are active the pin P(1) is driven to VCC P(0) is driven to VSS P(Z) floats P(Q) remains active(1) P(X) retains current state A( ) H( ) R( ) P( ) Figure 7 Example Pin Description Entry NOTE 1 Any pin that specifies P(Q) are valid for Idle Mode All pins are P(X) for Powerdown Mode 14 M80C186EB Table 4 M80C186EB Pin Descriptions Name VCC VSS CLKIN I A(E) Type Description POWER connections consist of four pins which must be shorted externally to a VCC board plane GROUND connections consist of six pins which must be shorted externally to a VSS board plane CLocK INput is an input for an external clock An external oscillator operating at two times the required M80C186EB operating frequency can be connected to CLKIN For crystal operation CLKIN (along with OSCOUT) are the crystal connections to an internal Pierce oscillator OSCillator OUTput is only used when using a crystal to generate the external clock OSCOUT (along with CLKIN) are the crystal connections to an internal Pierce oscillator This pin is not to be used as 2X clock output for non-crystal applications (i e this pin is N C for non-crystal applications) OSCOUT does not float in ONCE mode CLocK OUTput provides a timing reference for inputs and outputs of the processor and is one-half the input clock (CLKIN) frequency CLKOUT has a 50% duty cycle and transistions every falling edge of CLKIN RESet IN causes the M80C186EB to immediately terminate any bus cycle in progress and assume an initialized state All pins will be driven to a known state and RESOUT will also be driven active The rising edge (low-to-high) transition synchronizes CLKOUT with CLKIN before the M80C186EB begins fetching opcodes at memory location 0FFFF0H RESet OUTput that indicates the M80C186EB is currently in the reset state RESOUT will remain active as long as RESIN remains active Power-Down TiMeR pin (normally connected to an external capacitor) that determines the amount of time the M80C186EB waits after an exit from power down before resuming normal operation The duration of time required will depend on the startup characteristics of the crystal oscillator Non-Maskable Interrupt input causes a TYPE-2 interrupt to be serviced by the CPU NMI is latched internally TEST is used during the execution of the WAIT instruction to suspend CPU operation until the pin is sampled active (LOW) TEST is alternately known as BUSY when interfacing with an M80C187 numerics coprocessor These pins provide a multiplexed Address and Data bus During the address phase of the bus cycle address bits 0 through 15 are presented on the bus and can be latched using ALE 8- or 16-bit data information is transferred during the data phase of the bus cycle These pins provide multiplexed Address during the address phase of the bus cycle Address bits 16 through 19 are presented on these pins and can be latched using ALE These pins are driven to a logic 0 during the data phase of the bus cycle During a processor reset (RESIN active) A19 ONCE is used to enable ONCE mode A18 16 must not be driven low during reset or improper M80C186EB operation may result 15 OSCOUT O H(Q) R(Q) P(Q) O H(Q) R(Q) P(Q) I A(L) CLKOUT RESIN RESOUT O H(0) R(1) P(0) IO A(L) H(WH) R(Z) P(1) I A(E) I A(E) PDTMR NMI TEST BUSY AD15 0 IO S(L) H(Z) R(Z) P(X) H(Z) R(WH) P(X) A18 16 A19 ONCE M80C186EB Table 4 M80C186EB Pin Descriptions (Continued) Name S2 0 Type O H(Z) R(Z) P(1) Description Bus cycle Status are encoded on these pins to provide bus transaction information S2 0 are encoded as follows Bus Cycle Initiated S2 S1 S0 0 0 0 Interrupt Acknowledge 0 0 1 Read I O 0 1 0 Write I O 0 1 1 Processor HALT 1 0 0 Queue Instruction Fetch 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive (no bus activity) Address Latch Enable output is used to strobe address information into a transparent type latch during the address phase of the bus cycle ALE O H(0) R(0) P(0) O H(Z) R(Z) P(X) BHE Byte High Enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data bus BHE and A0 have the following logical encoding A0 BHE Encoding 0 0 Word Transfer 0 1 Even Byte Transfer 1 0 Odd Byte Transfer 1 1 Refresh Operation ReaD output signals that the accessed memory or I O device must drive data information onto the data bus RD O H(Z) R(Z) P(1) O H(Z) R(Z) P(1) I A(L) S(L) O H(Z) R(Z) P(1) O H(Z) R(Z) P(X) IO H(Z) R(WH) P(1) WR WRite output signals that data available on the data bus are to be written into the accessed memory or I O device READY READY input to signal the completion of a bus cycle READY must be active to terminate any M80C186EB bus cycle unless it is ignored by correctly programming the Chip-Select Unit Data ENable output to control the enable of bi-directional transceivers when buffering a M80C186EB system DEN is active only when data is to be transferred on the bus Data Transmit Receive output controls the direction of a bi-directional buffer when buffering an M80C186EB system DEN DT R LOCK LOCK output indicates that the bus cycle in progress is not to be interrupted The M80C186EB will not service other bus requests (such as HOLD) while LOCK is active This pin is configured as a weakly held high input while RESIN is active and must not be driven low 16 M80C186EB Table 4 M80C186EB Pin Descriptions (Continued) Name HOLD Type I A(L) O H(1) R(0) P(0) O H(1) R(1) P(1) I A(L) I A(L) O H(1) R(1) P(1) O H(1) R(1) P(1) GCS0 GCS1 GCS2 GCS3 GCS4 GCS5 GCS6 GCS7 O H(X) H(1) R(1) P(X) P(1) Description HOLD request input to signal that an external bus master wishes to gain control of the local bus The M80C186EB will relinquish control of the local bus between instruction boundaries not conditioned by a LOCK prefix HoLD Acknowledge output to indicate that the M80C186EB has relinquish control of the local bus When HLDA is asserted the M80C186EB will (or has) floated its data bus and control signals allowing another bus master to drive the signals directly Numerics Coprocessor Select output is generated when accessing a numerics coprocessor HLDA NCS ERROR ERROR input that indicates the last numerics coprocessor operation resulted in an exception condition An interrupt TYPE 16 is generated if ERROR is sampled active at the beginning of a numerics operation CoProcessor REQuest signals that a data transfer between an External Numerics Coprocessor and Memory is pending Upper Chip Select will go active whenever the address of a memory or I O bus cycle is within the address limitations programmed by the user After reset UCS is configured to be active for memory accesses between 0FFC00H and 0FFFFFH Lower Chip Select will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user LCS is inactive after a reset These pins provide a multiplexed function If enabled each pin can provide a Generic Chip Select output which will go active whenever the address of a memory or I O bus cycle is within the address limitations programmed by the user When not programmed as a Chip-Select each pin may be used as a general purpose output Port As an output port pin the value of the pin can be read internally PEREQ UCS LCS P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 T0OUT T1OUT O H(Q) R(1) P(Q) I A(L) A(E) Timer OUTput pins can be programmed to provide a single clock or continuous waveform generation depending on the timer mode selected T0IN T1IN Timer INput is used either as clock or control signals depending on the timer mode selected 17 M80C186EB Table 4 M80C186EB Pin Descriptions (Continued) Name INT0 INT1 INT4 INT2 INTA0 INT3 INTA1 Type I A(E L) IO A(E L) H(1) R(Z) P(1) IO A(L) H(X) R(Z) P(X) I A(L) O H(X) H(Q) R(1) P(X) P(Q) IO A(L) R(Z) H(Q) P(X) I A(L) A(E) Description Maskable INTerrupt input will cause a vector to a specific Type interrupt routine To allow interrupt expansion INT0 and or INT1 can be used with INTA0 and INTA1 to interface with an external slave controller These pins provide a multiplexed function As inputs they provide a maskable INTerrupt that will cause the CPU to vector to a specific Type interrupt routine As outputs each is programmatically controlled to provide an INTERRUPT ACKNOWLEDGE handshake signal to allow interrupt expansion Bidirectional open-drain Port pins P2 7 P2 6 CTSO P2 4 CTS1 TXD0 P2 1 TXD1 Clear-To-Send input is used to prevent the transmission of serial data on their respective TXD signal pin CTS1 is multiplexed with an input only port function Transmit Data output provides serial data information TXD1 is multiplexed with an output only Port function During synchronous serial communications TXD will function as a clock output Receive Data input accepts serial data information RXD1 is multiplexed with an input only Port function During synchronous serial communications RXD is bi-directional and will become an output for transmission or data (TXD becomes the clock) Baud CLocK input can be used as an alternate clock source for each of the integrated serial channels BCLKx is multiplexed with an input only Port function and cannot exceed a clock rate greater than one-half the operating frequency of the M80C186EB Serial INTerrupt output will go active to indicate serial channel 1 requires service SINT1 is multiplexed with an output only Port function RXD0 P2 0 RXD1 P2 5 BCLK0 P2 2 BCLK1 P2 3 SINT1 O H(X) H(Q) R(0) P(X) P(Q) 18 M80C186EB component Figure 8 depicts the complete M80C186EB pinout as viewed from the bottom side of the component M80C186EB PINOUT Table 5 lists the M80C186EB pin names with package location for the 88-Lead Pin Grid Array (PGA) Table 5 MG80C186EB Pin Assignments PLCC PGA 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 1A 2B 1B 2C 1C 2D 1D 2E 1E 2F 1F 2G 1G 2H 1H 2J 1J 2K 1K 2L 1L 2M Name DEN S0 S1 S2 BHE ALE WR RD ERROR VSS VCC VSS A19 ONCE A18 A17 A16 AD15 AD7 AD14 AD6 AD13 NC 62 61 60 59 58 57 56 55 54 PLCC PGA 74 73 72 71 70 69 68 67 66 65 64 63 Name PLCC PGA 12N 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 13N 13M 12L 13L 12K 13K 12J 13J 12H 13H 12G 13G 12F 13F 12E 13E 12D 13D 12C 13C 12B Name NC RXD0 TXD0 CTS0 P2 6 P2 7 T1IN T1OUT T0IN T0OUT CLKOUT VSS VCC CLKIN OSCOUT PEREQ RESOUT RESIN PDTMR INT4 INT3 INT2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 PLCC PGA Name 1M AD5 1N AD12 2N AD4 3M AD11 3N AD3 4M AD10 4N AD2 5M AD9 5N AD1 6M VSS 6N VCC 7M VSS 7N N C 8M AD8 8N AD0 9M NCS 9N P2 2 BCLK1 10M P2 1 TXD1 10N P2 0 RXD1 11M P2 4 CTS1 11N P2 3 SINT1 12M P2 5 BLCK0 13B N C 13A INT1 12A INT0 11B UCS 11A LCS 10B P1 0 GCS0 10A P1 1 GCS1 9B P1 2 GCS2 9A P1 3 GCS3 8B P1 4 GCS4 8A VCC 7B VSS 7A P1 5 GCS5 6B P1 6 GCS6 6A P1 7 GCS7 5B READY 5A NMI 4B DRT R 4A LOCK 3B TEST BUSY 3A HOLD 2A HLDA 19 M80C186EB Pin Grid Array 271214 - 6 Figure 8 20 M80C186EB ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Storage Temperature Case Temp Under Bias Supply Voltage with respect to VSS Voltage on other Pins with respect to VSS Maximum Rating b 65 C to a 150 C b 55 C to a 125 C b 0 5V to a 6 5V b 0 5V to VCC a 0 5V NOTICE This data sheet contains information on products in the sampling and initial production phases of development It is valid for the devices indicated in the revision history The specifications are subject to change without notice WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability OPERATING CONDITIONS Symbol VCC TF Parameter Supply Voltage Input Clock Frequency M80C186EB-16 M80C186EB-13 M80C186EB-8 TC Case Temperature Under Bias Min 45 0 0 0 b 55 Max 55 32 26 08 16 a 125 Units V MHz MHz MHz C RECOMMENDED CONNECTIONS Power and ground connections must be made to multiple VCC and VSS pins Every M80C186EBbased circuit board should include separate power (VCC) and ground (VSS) planes Every VCC pin must be connected to the power plane and every VSS pin must be connected to the ground plane Pins identified as ``NC'' must not be connected in the system Liberal decoupling capacitance should be placed near the M80C186EB The processor can cause transient power surges when its output buffers transition particularly when connected to large capacitive loads Low inductance capacitors and interconnects are recommended for best high frequency electrical performance Inductance is reduced by placing the decoupling capacitors as close as possible to the M80C186EB VCC and VSS package pins Always connect any unused input to an appropriate signal level In particular unused interrupt inputs (INT0 4) should be connected to VCC through a pullup resistor (in the range of 50 KX) Leave any unused output pin or any NC pin unconnected 21 M80C186EB DC SPECIFICATIONS Symbol VIL VIH VOL VOH VHYR ILI1 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Hysterisis on RESIN Input Leakage Current for pins AD15 0 READY HOLD RESIN TEST NMI INT4 0 T0IN T1IN RXD0 BCLK0 CTS0 RXD1 BCLK1 CTS1 P2 6 P2 7 Input Leakage Current for Pin CLKIN Input Current for Pin ERROR Input Current for Pin PEREQ Output Leakage Current Supply Current Cold (RESET) M80C186EB-16 M80C186EB-13 M80C186EB-8 IID Supply Current Idle M80C186EB-16 M80C186EB-13 M80C186EB-8 IPD Supply Current Powerdown M80C186EB-16 M80C186EB-13 M80C186EB-8 CIN COUT Input Pin Capacitance Output Pin Capacitance 0 0 b7 a 0 275 Min b0 5 Max 0 3 VCC VCC a 0 5 0 45 Units V V V V V Notes (Note 8) 0 7 VCC VCC b 0 5 0 50 IOL e 3 mA (Min) IOH e b 2 mA (MIn) g15 mA 0V s VIN s VCC ILI2 II1 II2 ILO ICC g50 mA mA mA mA 0V s VIN s VCC VIN e 0V VIN e VCC 0 45 s VOUT s VCC (Notes 2 7) (Note 3) (Note 3) (Note 3) (Note 4) (Note 4) (Note 4) (Note 5) (Note 5) (Note 5) TF e 1 MHz TF e 1 MHz (Note 6) b 0 275 a7 g15 90 73 45 63 48 31 100 100 100 15 15 mA mA mA mA mA mA mA mA mA pF pF NOTES 1 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more current than specified (on any of these pins) may invoke a factory test mode 2 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD 3 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 4 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 5 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 6 Output Capacitance is the capacitive load of a floating output pin 7 OSC out is not tested 8 A19 ONCE A18 16 LOCK are not tested 22 M80C186EB ICC VERSUS FREQUENCY AND VOLTAGE The current (ICC) consumption of the M80C186EB is essentially composed of two components IPD and ICCS IPD is the quiescent current that represents internal device leakage and is measured with all inputs or floating outputs at GND or VCC (no clock applied to the device) IPD is equal to the Powerdown current and is typically less than 50 mA ICCS is the switching current used to charge and discharge parasitic device capacitance when changing logic levels Since ICCS is typically much greater than IPD IPD can often be ignored when calculating ICC ICCS is related to the voltage and frequency at which the device is operating It is given by the formula Power e V c I e V2 c CDEV c f I e ICC e ICCS e V c CDEV c f Where V e Device operating voltage (VCC) CDEV e Device capacitance f e Device operating frequency ICCS e ICC e Device current Measuring CDEV on a device like the M80C186EB would be difficult Instead CDEV is calculated using the above formula by measuring ICC at a known VCC and frequency (see Table 11) Using this CDEV value ICC can be calculated at any voltage and frequency within the specified operating range EXAMPLE Calculate the typical ICC when operating at 10 MHz 4 8V ICC e ICCS e 4 8 c 0 583 c 10 28 mA PDTMR PIN DELAY CALCULATION The PDTMR pin provides a delay between the assertion of NMI and the enabling of the internal clocks when exiting Powerdown A delay is required only when using the on-chip oscillator to allow the crystal or resonator circuit time to stabilize NOTE The PDTMR pin function does not apply when RESIN is asserted (i e a device reset during Powerdown is similar to a cold reset and RESIN must remain active until after the oscillator has stabilized) To calculate the value of capacitor required to provide a desired delay use the equation 440 c t e CPD (5V 25 C) Where t e desired delay in seconds CPD e capacitive load on PDTMR in microfarads EXAMPLE To get a delay of 300 ms a capacitor value of CPD e 440 c (300 c 10b6) e 0 132 mF is required Round up to standard (available) capacitive values NOTE The above equation applies to delay times greater than 10 ms and will compute the TYPICAL capacitance needed to achieve the desired delay A delay variance of a 50% or b 25% can occur due to temperature voltage and device process extremes In general higher VCC and or lower temperature will decrease delay time while lower VCC and or higher temperature will increase delay time Table 11 Device Capacitance (CDEV) Values Parameter CDEV (Device in Reset) CDEV (Device in Idle) Typ 0 583 0 408 Max 1 02 0 682 Units mA V MHz mA V MHz Notes 12 12 1 Max CDEV is calculated at b40 C all floating outputs driven to VCC or GND and all outputs loaded to 50 pF (including CLKOUT and OSCOUT) 2 Typical CDEV is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and OSCOUT which are not loaded 23 M80C186EB AC SPECIFICATIONS AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 TCHOV2 TCLOV1 TCLOV2 TCHOF TCLOF TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time ALE S2 0 DEN DT R BHE LOCK A19 16 GCS0 7 LCS UCS NCS RD WR BHE DEN LOCK RESOUT HLDA T0OUT T1OUT A19 16 RD WR GCS7 0 LCS UCS AD15 0 NCS INTA1 0 S2 0 RD WR BHE DT R LOCK S2 0 A19 16 DEN AD15 0 TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 AD15 0 READY READY AD15 0 HOLD PEREQ ERROR HOLD PEREQ ERROR 0 31 25 10 10 1 1 0 (T 2) b 5 (T 2) b 5 32 % % % 8 8 20 2 TC (T 2) a 5 (T 2) a 5 6 6 22 27 22 27 25 25 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 12 12 1 3 11 1 3 11 14 1 1 1 15 15 1467 1468 146 146 1 11 1 11 19 19 1 10 1 10 19 19 M80C186EB-16 Parameter Min Max Units Notes OUTPUT CLOCK OUTPUT DELAYS 1 1 1 1 0 0 10 3 10 3 10 3 SYNCHRONOUS INPUTS NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 16 for capacitive derating information 5 Specified for a 50 pF load see Figure 17 for rise and fall times outside 50 pF 6 See Figure 17 for rise and fall times 7 TCHOV1 applies to BHE LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper M80C186EB operation 11 Not tested 24 M80C186EB AC SPECIFICATIONS AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 TCHOV2 TCLOV1 TCLOV2 TCHOF TCLOF TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time ALE S2 0 DEN DT R BHE LOCK A19 16 GCS0 7 LCS UCS NCS RD WR BHE DEN LOCK RESOUT HLDA T0OUT T1OUT A19 16 RD WR GCS7 0 LCS UCS AD15 0 NCS INTA1 0 S2 0 RD WR BHE DT R LOCK S2 0 A19 16 DEN AD15 0 TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 AD15 0 READY READY AD15 0 HOLD PEREQ ERROR HOLD PEREQ ERROR 0 38 34 12 12 1 1 0 (T 2) b 5 (T 2) b 5 26 08 % % % 8 8 23 2 TC (T 2) a 5 (T 2) a 5 6 6 25 30 25 30 25 25 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 12 12 13 13 14 1 1 1 15 15 1467 1468 146 146 1 11 1 11 19 19 1 10 1 10 19 19 M80C186EB-13 Parameter Min Max Units Notes OUTPUT CLOCK OUTPUT DELAYS 1 1 1 1 0 0 10 3 10 3 10 3 SYNCHRONOUS INPUTS NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 16 for capacitive derating information 5 Specified for a 50 pF load see Figure 17 for rise and fall times outside 50 pF 6 See Figure 17 for rise and fall times 7 TCHOV1 applies to BHE LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper M80C186EB operation 11 Not tested 25 M80C186EB AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 TCHOV2 TCLOV1 TCLOV2 TCHOF TCLOF TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH M80C186EB-8 Parameter Min 0 62 5 15 15 1 1 0 (T 2) b 5 (T 2) b 5 Max 16 % % % 8 8 27 2 TC (T 2) a 5 (T 2) a 5 6 6 30 35 30 35 30 35 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 12 12 13 13 14 1 1 1 15 15 1467 1468 146 146 1 11 1 11 19 19 1 10 1 10 19 19 CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time ALE S2 0 DEN DT R BHE LOCK A19 16 GCS0 7 LCS UCS NCS RD WR BHE DEN LOCK RESOUT HLDA T0OUT T1OUT A19 16 RD WR GCS7 0 LCS UCS AD15 0 NCS INTA1 0 S2 0 RD WR BHE DT R LOCK S2 0 A19 16 DEN AD15 0 TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 AD15 0 READY READY AD15 0 HOLD PEREQ ERROR HOLD PEREQ ERROR OUTPUT CLOCK OUTPUT DELAYS 1 1 1 1 0 0 10 3 10 3 10 3 SYNCHRONOUS INPUTS NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 16 for capacitive derating information 5 Specified for a 50 pF load see Figure 17 for rise and fall times outside 50 pF 6 See Figure 17 for rise and fall times 7 TCHOV1 applies to BHE LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper M80C186EB operation 11 Not tested 26 M80C186EB Relative Timings (M80C186EB-16 -13 -8) Symbol RELATIVE TIMINGS TLHLL TAVLL TPLLL TLLAX TLLWL TLLRL TWHLH TAFRL TRLRH TWLWH TRHAV TWHDX TWHPH TRHPH TPHPL TOVRH TRHOX ALE Rising to ALE Falling Address Valid to ALE Falling Chip Selects Valid to ALE Falling Address Hold from ALE Falling ALE Falling to WR Falling ALE Falling to RD Falling WR Rising to ALE Rising Address Float to RD Falling RD Falling to RD Rising WR Falling to WR Rising RD Rising to Address Active Output Data Hold after WR Rising WR Rising to Chip Select Rising RD Rising to Chip Select Rising CS Inactive to CS Active ONCE Active to RESIN Rising ONCE Hold from RESIN Rising T b 15 T b 10 T b 10 T b 10 T b 15 T b 15 T b 10 0 (2 T) b 5 (2 T) b 5 T b 15 T b 15 T b 10 T b 10 T b 10 T T ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 3 3 2 2 1 1 1 1 Parameter Min Max Unit Notes NOTES 1 Assumes equal loading on both pins 2 Can be extended using wait states 3 Not tested 27 M80C186EB Serial Port Mode 0 Timings (M80C186EB-16 -13 -8) Symbol TXLXL TXLXH TXLXH TXHXL TXHXL TQVXH TQVXH TXHQX TXHQX TXHQZ TDVXH TXHDX TXD Clock Period TXD Clock Low to Clock High (n l 1) TXD Clock Low to Clock High (n e 1) TXD Clock High to Clock Low (n l 1) TXD Clock High to Clock Low (n e 1) RXD Output Data Setup to TXD Clock High (n l 1) RXD Output Data Setup to TXD Clock High (n e 1) RXD Output Data Hold after TXD Clock High (n l 1) RXD Output Data Hold after TXD Clock High (n e 1) RXD Output Data Float after Last TXD Clock High RXD Input Data Setup to TXD Clock High RXD Input Data Hold after TXD Clock High T a 20 0 Parameter Min T (n a 1) 2T b 35 T b 35 2T a 35 T a 35 Max Unit Notes ns ns ns ns ns ns ns ns ns T a 20 ns ns ns 12 1 1 12 1 12 1 1 1 13 1 13 (n b 1) T b 35 (n b 1) T a 35 T b 35 (n b 1) T b 35 T b 35 2T b 35 T b 35 T a 35 NOTES 1 See Figure 14 for waveforms 2 n is the value of the BxCMP register ignoring the ICLK Bit (i e ICLK e 0) 3 Guaranteed not tested 28 M80C186EB AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 9 See the Derating Curves section to see how timings vary with load capacitance Specifications are measured at the VCC 2 crossing point unless otherwise specified See AC Timing Waveforms for AC specification definitions test pins and illustrations CL e 50 pF for all signals 271214 - 7 Figure 9 AC Test Load AC TIMING WAVEFORMS 271214 - 8 Figure 10 Input and Output Clock Waveform 29 M80C186EB 271214 - 9 NOTE 20% VCC k Float k 80% VCC Figure 11 Output Delay and Float Waveform 271214 - 10 Figure 12 Input Setup and Hold 30 M80C186EB 271214 - 11 Figure 13 Relative Signal Waveform 271214 - 12 Figure 14 Serial Port Mode 0 Waveform 31 M80C186EB DERATING CURVES TYPICAL OUTPUT DELAY VARIATIONS VERSUS LOAD CAPACITANCE 271214 - 13 Figure 15 TYPICAL RISE AND FALL VARIATIONS VERSUS LOAD CAPACITANCE 271214 - 14 Figure 16 32 M80C186EB must ensure that the ramp time for VCC is not so long that RESIN is never really sampled at a logic low level when VCC reaches minimum operating conditions Figure 18 shows the timing sequence when RESIN is applied after VCC is stable and the device has been operating Note that a reset will terminate all activity and return the M80C186EB to a known operating state Any bus operation that is in progress at the time RESIN is asserted will terminate immediately (note that most control signals will be driven to their inactive state first before floating) While RESIN is active bus signals LOCK A19 ONCE and A18 16 are configured as inputs and weakly held high by internal pullup transistors Only 19 ONCE can be overdriven to a low and is used to enable ONCE Mode Forcing LOCK or A18 16 low at any time while RESIN is low is prohibited and will cause unspecified device operation RESET The M80C186EB will perform a reset operation any time the RESIN pin active The RESIN pin is actually synchronized before it is presented internally which means that the clock must be operating before a reset can take effect From a power-on state RESIN must be held active (low) in order to guarantee correct initialization of the M80C186EB Failure to provide RESIN while the device is powering up will result in unspecified operation of the device Figure 17 shows the correct reset sequence when first applying power to the M80C186EB An external clock connected to CLKIN must not exceed the VCC threshold being applied to the M80C186EB This is normally not a problem if the clock driver is supplied with the same VCC that supplies the M80C186EB When attaching a crystal to the device RESIN must remain active until both VCC and CLKOUT are stable (the length of time is application specific and depends on the startup characteristics of the crystal circuit) The RESIN pin is designed to operate correctly using an RC reset circuit but the designer 33 34 271214- 15 M80C186EB COLD RESET WAVEFORMS Figure 17 NOTE CLKOUT synchronization occurs on the rising edge of RESIN If RESIN is sampled high while CLKOUT is high (solid line) then CLKOUT will remain low for two CLKIN periods If RESIN is sampled high while CLKOUT is low (dashed line) then CLKOUT will not be affected M80C186EB WARM RESET WAVEFORMS 271214- 16 Figure 18 35 M80C186EB and I O bus cycles The only variation among the different bus cycles would be the range of address generated and the state of the status signals The Halt bus cycle is shown in Figure 22 Note that the condition of the AD15 0 pin can be either floating or driving depending on the operation of the bus cycle that preceded the Halt The pins will float if the previous bus cycle was a read otherwise they will drive None of the control signals (e g RD WR DEN etc ) will be activated however Figure 23 shows the sequence of bus cycles run when an interrupt is acknowledged and the ICU has been programmed for Cascade Mode Note the address information is not valid for the two bus cycles run however also note that RD and WR are not generated Vector information needs to be returned during the second bus cycle Figures 24 and 25 present the operation of bus HOLD Figure 24 shows how bus HOLD is entered and exited under normal operating conditions Figure 25 shows the effect specific bus signals have when a refresh bus cycle request has been generated and the bus is currently unavailable due to a bus HOLD The effects of READY on bus operation is shown in Figure 26 READY is useful in extending the bus cycle to meet the various access requirements for memory and peripheral devices in the system Additional T3 states added to the bus cycle have been appropriately labeled Tw BUS CYCLE WAVEFORMS Figures 19 through 25 present the various bus cycles that are generated by the M80C186EB What is shown in the figure is the relationship of the various bus signals to CLKOUT These figures along with the information present in AC Specifications allow the user to determine all the critical timing analysis needed for a given application Figure 19 shows the M80C186EB bus state diagram A typical bus cycle will consist of four consecutive states labeled T1 T2 T3 and T4 A TI state exists when no bus cycle is pending A TI state can occur if the pre-fetch queue is full the BIU is waiting for the completion of an effective address calculation or the BIU is told to wait for a pending EU bus operation The latter case will occur most often during the sequencing of an interrupt acknowledge or during the execution of numerics escape instructions Aside from TI states multiple T3 states can occur during a bus cycle if READY is not returned in time (or the CSU has been programmed to automatically insert wait-states) A T3 state will be followed by either a T4 state (if a bus cycle is pending) or a TI state (if no bus cycle is pending) Only multiple T3 or TI states can exist (i e there is no way to extend the T1 T2 or T4 states) Figures 20 and 21 present a typical bus read and write operation respectively Bus read operations include memory I O instruction fetch and refresh bus cycles Bus write operations include memory 271214 - 17 Figure 19 M80C186EB Bus States 36 M80C186EB MEMORY READ I O READ INSTRUCTION FETCH AND REFRESH WAVEFORM 271214 - 18 Figure 20 37 M80C186EB MEMORY WRITE AND I O WRITE CYCLE WAVEFORM 271214 - 19 Figure 21 38 M80C186EB HALT CYCLE WAVEFORM 271214 - 20 NOTE The address driven is typically the location of the next instruction prefetch Under a majority of instruction sequences the AD15 0 bus will float while the A19 16 bus remains driven and all bus control signals are driven to their inactive state Figure 22 39 M80C186EB CASCADE MODE INTERRUPT ACKNOWLEDGE CYCLE WAVEFORM 271214 - 21 Figure 23 40 M80C186EB HOLD HLDA CYCLE WAVEFORMS 271214 - 22 Figure 24 41 M80C186EB REFRESH DURING HLDA CYCLE WAVEFORM 271214 - 23 NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Figure 25 42 M80C186EB READY CYCLE WAVEFORM 271214 - 24 NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Figure 26 43 M80C186EB The Timer Counter Unit registers are presented in Figure 29 The compare and count registers are not initialized after reset and must be set correctly during initialization to ensure the timer operates correctly the first time it is enabled Figure 30 presents the I O Port Unit (IPU) registers Only PD6 and PD7 or of the P2DIR register have any effect on the direction of the port pins (P2 6 and P2 7 respectively) The unused bits of P2DIR and all the bits of P1DIR can be thought of having latches that can be read and written The two PxLTCH registers have all 8-bits implemented however only those port pins which can function as outputs actually use the value programmed into the latch Otherwise (like the P1DIR register) the registers can be thought of being an 8-bit data register Figure 31 presents the register bit definitions of the Serial Communications Unit (SCU) The transmit and receive buffer registers are both readable and writeable Note that a read from SxSTS register will clear all of the status information (except for CTS which actually is derived from the pin itself) The Chip-Select Unit (CSU) registers are presented in Figure 32 and the Refresh Control Unit (RCU) registers are presented in Figure 33 The RFADDR register will indicate the current refresh address when read and a write to the register will change the next refresh address generated Figure 34 presents the PWRCON register and STEPID register The STEPID register contains a stepping identifier that may or may not change any time there is a change to the M80C186EB silicon die The STEPID is for Intel use and can change at any time REGISTER BIT SUMMARY Figures 27 through 34 present the bit definition of each register that is active (not reserved) in the Peripheral Control Block (PCB) Each register can be thought to occupy one word (16-bits) of either memory or I O space although not all bits in the register necessarily have a function A register bit is not guaranteed to return a specific logic value if an ``X'' appears for the bit definition (i e if a zero was written to the register bit it may not be returned as a zero when read) Furthermore a 0 must be written to any bit that is indicated by an ``X'' to ensure compatibility with future products or potential product changes Not all defined register bits can be read and or written although most registers are read write Some registers like the P1DIR register exist but do not have any effect on the operation of the M80C186EB For example the Port1 pins are output only and cannot be changed by programming the P1DIR register However the P1DIR register can still be read and written which allows the P1DIR register to be used as a temporary 8-bit data register Reads and writes to any of the PCB registers will cause a bus cycle to be run externally however none of the chip selects will go active (even if they overlap the PCB address range) Data read back from the AD15 0 bus is ignored and all cycles will take zero wait states (except accesses to the Timer Counter registers which take one wait state due to internal synchronization) Figures 27 and 28 present the registers associated with the Interrupt Control Unit (ICU) A write to the MASK (08H) register will also effect the corresponding MSK bit in each of the control registers (e g setting the TMR bit in the MASK register will also set the MSK bit in the TMRCON register) 44 M80C186EB 271214 - 25 Figure 27 Interrupt Control Unit Registers 271214 - 26 Figure 28 Interrupt Control Unit Registers 45 M80C186EB 271214 - 27 Figure 29 Timer Control Unit Registers 271214 - 28 Figure 30 I O Port Unit Registers 46 M80C186EB 271214 - 29 Figure 31 Serial Communications Unit Registers 271214 - 30 Figure 32 Chip-Select Unit Registers 47 M80C186EB 271214 - 31 Figure 33 Refresh Control Unit Registers 271214 - 32 Figure 34 Power Management Unit Registers M80C186EB EXECUTION TIMINGS A determination of M80C186EB program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of execution unit cycles necessary to execute instructions The following instruction timings represent the minimum execution time in clock cycles for each instruction The timings given are based on the following assumptions All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address All instructions which involve memory accesses can require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit With a 16-bit BIU the M80C186EB has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue most of the time Therefore actual program execution time will not be substantially greater than that derived from adding the instruction timings shown The opcode along with any data or displacement required for execution of a particular instruction has been prefetched and resides in the queue at the time it is needed No wait states or bus HOLDs occur All word-data is located on even-address boundaries 48 M80C186EB INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV e Move Register to Register Memory Register memory to register Immediate to register memory Immediate to register Memory to accumulator Accumulator to memory Register memory to segment register Segment register to register memory PUSH e Push Memory Register Segment register Immediate PUSHA e Push All POP e Pop Memory Register Segment register POPA e Pop All XCHG e Exchange Register memory with register Register with accumulator IN e Input from Fixed port Variable port OUT e Output to Fixed port Variable port XLAT e Translate byte to AL LEA e Load EA to register LDS e Load pointer to DS LES e Load pointer to ES LAHF e Load AH with flags SAHF e Store AH into flags PUSHF e Push flags POPF e Pop flags 1110011w 1110111w 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101 mod reg r m mod reg r m mod reg r m (mod i 11) (mod i 11) port 9 7 11 6 18 18 2 3 9 8 1110010w 1110110w port 10 8 1000011w 1 0 0 1 0 reg mod reg r m 4 17 3 10001111 0 1 0 1 1 reg 0 0 0 reg 1 1 1 01100001 (reg i 01) mod 0 0 0 r m 20 10 8 51 11111111 0 1 0 1 0 reg 0 0 0 reg 1 1 0 011010s0 01100000 data data if s e 0 mod 1 1 0 r m 16 10 9 10 36 1000100w 1000101w 1100011w 1 0 1 1 w reg 1010000w 1010001w 10001110 10001100 mod reg r m mod reg r m mod 000 r m data addr-low addr-low mod 0 reg r m mod 0 reg r m data data if w e 1 addr-high addr-high data if w e 1 2 12 29 12 - 13 3-4 8 9 29 2 11 8 16-bit 8 16-bit Format Clock Cycles Comments Shaded areas indicate instructions not available in M8086 M8088 microsystems 49 M80C186EB INSTRUCTION SET SUMMARY (Continued) Function DATA TRANSFER (Continued) SEGMENT e Segment Override CS SS DS ES ARITHMETIC ADD e Add Reg memory with register to either Immediate to register memory Immediate to accumulator ADC e Add with carry Reg memory with register to either Immediate to register memory Immediate to accumulator INC e Increment Register memory Register SUB e Subtract Reg memory and register to either Immediate from register memory Immediate from accumulator SBB e Subtract with borrow Reg memory and register to either Immediate from register memory Immediate from accumulator DEC e Decrement Register memory Register CMP e Compare Register memory with register Register with register memory Immediate with register memory Immediate with accumulator NEG e Change sign register memory AAA e ASCII adjust for add DAA e Decimal adjust for add AAS e ASCII adjust for subtract DAS e Decimal adjust for subtract MUL e Multiply (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word 0011101w 0011100w 100000sw 0011110w 1111011w 00110111 00100111 00111111 00101111 1111011w mod 100 r m 26- 28 35- 37 32- 34 41- 43 mod reg r m mod reg r m mod 1 1 1 r m data mod 0 1 1 r m data data if w e 1 data if s w e 01 3 10 3 10 3 10 34 3 10 8 4 7 4 8 16-bit 1111111w 0 1 0 0 1 reg mod 0 0 1 r m 3 15 3 000110dw 100000sw 0001110w mod reg r m mod 0 1 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 8 16-bit 001010dw 100000sw 0010110w mod reg r m mod 1 0 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 8 16-bit 1111111w 0 1 0 0 0 reg mod 0 0 0 r m 3 15 3 000100dw 100000sw 0001010w mod reg r m mod 0 1 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 8 16-bit 000000dw 100000sw 0000010w mod reg r m mod 0 0 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 8 16-bit 00101110 00110110 00111110 00100110 2 2 2 2 Format Clock Cycles Comments Shaded areas indicate instructions not available in M8086 M8088 microsystems 50 M80C186EB INSTRUCTION SET SUMMARY (Continued) Function ARITHMETIC (Continued) IMUL e Integer multiply (signed) Register-Byte Register-Word Memory-Byte Memory-Word IMUL e Integer Immediate multiply (signed) DIV e Divide (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word IDIV e Integer divide (signed) Register-Byte Register-Word Memory-Byte Memory-Word AAM e ASCII adjust for multiply AAD e ASCII adjust for divide CBW e Convert byte to word CWD e Convert word to double word LOGIC Shift Rotate Instructions Register Memory by 1 Register Memory by CL Register Memory by Count 1101000w 1101001w 1100000w mod TTT r m mod TTT r m mod TTT r m TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHL SAL 101 SHR 111 SAR AND e And Reg memory and register to either Immediate to register memory Immediate to accumulator TEST e And function to flags no result Register memory and register Immediate data and register memory Immediate data and accumulator OR e Or Reg memory and register to either Immediate to register memory Immediate to accumulator 000010dw 1000000w 0000110w mod reg r m mod 0 0 1 r m data data data if w e 1 data if w e 1 3 10 4 16 34 8 16-bit 1000010w 1111011w 1010100w mod reg r m mod 0 0 0 r m data data data if w e 1 data if w e 1 3 10 4 10 34 8 16-bit 001000dw 1000000w 0010010w mod reg r m mod 1 0 0 r m data data data if w e 1 data if w e 1 3 10 4 16 34 8 16-bit count 2 15 5 a n 17 a n 5 a n 17 a n 11010100 11010101 10011000 10011001 00001010 00001010 1111011w mod 1 1 1 r m 44- 52 53- 61 50- 58 59- 67 19 15 2 4 011010s1 mod reg r m data data if s e 0 1111011w mod 1 0 1 r m 25- 28 34- 37 31- 34 40- 43 22 - 25 29- 32 Format Clock Cycles Comments 1111011w mod 1 1 0 r m 29 38 35 44 Shaded areas indicate instructions not available in M8086 M8088 microsystems 51 M80C186EB INSTRUCTION SET SUMMARY (Continued) Function LOGIC (Continued) XOR e Exclusive or Reg memory and register to either Immediate to register memory Immediate to accumulator NOT e Invert register memory STRING MANIPULATION MOVS e Move byte word CMPS e Compare byte word SCAS e Scan byte word LODS e Load byte wd to AL AX STOS e Store byte wd from AL AX INS e Input byte wd from DX port OUTS e Output byte wd to DX port 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 14 22 15 12 10 14 14 001100dw 1000000w 0011010w 1111011w mod reg r m mod 1 1 0 r m data mod 0 1 0 r m data data if w e 1 data if w e 1 3 10 4 16 34 3 10 8 16-bit Format Clock Cycles Comments Repeated by count in CX (REP REPE REPZ REPNE REPNZ) MOVS e Move string CMPS e Compare string SCAS e Scan string LODS e Load string STOS e Store string INS e Input string OUTS e Output string CONTROL TRANSFER CALL e Call Direct within segment Register memory indirect within segment Direct intersegment 11101000 11111111 disp-low mod 0 1 0 r m disp-high 15 13 19 11110010 1111001z 1111001z 11110010 11110010 11110010 11110010 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 10011010 segment offset segment selector 23 Indirect intersegment JMP e Unconditional jump Short long Direct within segment Register memory indirect within segment Direct intersegment 11111111 mod 0 1 1 r m (mod i 11) 38 11101011 11101001 11111111 disp-low disp-low mod 1 0 0 r m disp-high 14 14 11 17 11101010 segment offset segment selector 14 Indirect intersegment 11111111 mod 1 0 1 r m (mod i 11) 26 Shaded areas indicate instructions not available in M8086 M8088 microsystems 52 M80C186EB INSTRUCTION SET SUMMARY (Continued) Function CONTROL TRANSFER (Continued) RET e Return from CALL Within segment Within seg adding immed to SP Intersegment Intersegment adding immediate to SP JE JZ e Jump on equal zero JL JNGE e Jump on less not greater or equal JLE JNG e Jump on less or equal not greater JB JNAE e Jump on below not above or equal JBE JNA e Jump on below or equal not above JP JPE e Jump on parity parity even JO e Jump on overflow JS e Jump on sign JNE JNZ e Jump on not equal not zero JNL JGE e Jump on not less greater or equal JNLE JG e Jump on not less or equal greater JNB JAE e Jump on not below above or equal JNBE JA e Jump on not below or equal above JNP JPO e Jump on not par par odd JNO e Jump on not overflow JNS e Jump on not sign JCXZ e Jump on CX zero LOOP e Loop CX times LOOPZ LOOPE e Loop while zero equal LOOPNZ LOOPNE e Loop while not zero equal ENTER e Enter Procedure Le0 Le1 Ll1 LEAVE e Leave Procedure INT e Interrupt Type specified Type 3 INTO e Interrupt on overflow 11001101 11001100 11001110 type 47 45 48 4 if INT taken if INT not taken 11001001 11000011 11000010 11001011 11001010 01110100 01111100 01111110 01110010 01110110 01111010 01110 000 01111000 01110101 01111101 01111111 01110011 01110111 01111011 01110001 01111001 11100011 11100010 11100001 11100000 11001000 data-low disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp data-low data-high L 15 25 22 a 16(n b 1) 8 data-high data-low data-high 16 18 22 25 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 LOOP not taken LOOP taken JMP not taken JMP taken Format Clock Cycles Comments IRET e Interrupt return BOUND e Detect value out of range 11001111 01100010 mod reg r m 28 33- 35 Shaded areas indicate instructions not available in M8086 M8088 microsystems 53 M80C186EB INSTRUCTION SET SUMMARY (Continued) Function PROCESSOR CONTROL CLC e Clear carry CMC e Complement carry STC e Set carry CLD e Clear direction STD e Set direction CLI e Clear interrupt STI e Set interrupt HLT e Halt WAIT e Wait LOCK e Bus lock prefix NOP e No Operation 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11110000 10010000 (TTT LLL are opcode to processor extension) 2 2 2 2 2 2 2 2 6 2 3 if TEST e 0 Format Clock Cycles Comments Shaded areas indicate instructions not available in M8086 M8088 microsystems FOOTNOTES The Effective Address (EA) of the memory operand is computed according to the mod and r m fields if mod e 11 then r m is treated as a REG field if mod e 00 then DISP e 0 disp-low and disphigh are absent if mod e 01 then DISP e disp-low sign-extended to 16-bits disp-high is absent if mod e 10 then DISP e disp-high disp-low e 000 then EA e (BX) a (SI) a DISP if r m e 001 then EA e (BX) a (DI) a DISP if r m e 010 then EA e (BP) a (SI) a DISP if r m e 011 then EA e (BP) a (DI) a DISP if r m e 100 then EA e (SI) a DISP if r m e 101 then EA e (DI) a DISP if r m e 110 then EA e (BP) a DISP if r m e 111 then EA e (BX) a DISP if r m DISP follows 2nd byte of instruction (before data if required) except if mod e 00 and r m e 110 then EA e disp-high disp-low EA calculation time is 4 clock cycles for all modes and is included in the execution times given whenever appropriate Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following Segment reg Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table 16-Bit (w e 1) 8-Bit (w e 0) 000 AX 000 AL 001 CX 001 CL 010 DX 010 DL 011 BX 011 BL 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS segment register The physical addresses of the destination operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment which may not be overridden 54 M80C186EB 88-LEAD CERAMIC PIN GRID ARRAY PACKAGE 271214 - 33 Family Ceramic Pin Grid Array Package Symbol A A1 A2 A3 B D D1 e1 L N S1 ISSUE 1 27 IWS Millimeters Min 3 56 0 76 2 67 1 14 0 43 33 91 30 35 2 29 2 54 Max 4 57 1 27 3 43 1 40 0 51 34 67 30 61 2 79 3 30 88 2 54 10 12 88 0 050 Solid Lid Solid Lid Notes Min 0 140 0 030 0 105 0 045 0 017 1 335 1 195 0 090 0 100 Inches Max 0 180 0 050 0 135 0 055 0 020 1 365 1 205 0 110 0 130 88 0 100 Solid Lid Solid Lid Notes 55 M80C186EB ERRATA The current stepping (B step) of the M80C186EB has the following known functional anomaly An internal problem with the interrupt controller may prevent an acknowledge cycle from occurring on the INTA1 line after an interrupt on INT1 This error only occurs when INT1 is configured in cascaded mode and a higher priority interrupt exists Problem An interrupt acknowledge for INT1 is not generated on INTA1 in some conditions Condition Another interrupt of higher priority occurs after the decision is made to service Interrupt 1 but before the expected acknowledge cycle on INTA1 Configuration 1 Master mode 2 INT1 is in cascade mode and is enabled 3 An interrupt of higher priority than INT1 is enabled (i e DMA timers serial ports INT lines) Workaround There are only two possible situations that might cause this problem These with their corresponding workarounds are described in the table below Condition Only INT1 is configured in cascade mode and is also a lower priority than another interrupt INT1 and INT0 are both in cascade mode and INT1 is of lower priority than another interrupt Workaround Use INT0 in cascaded mode instead or make INT1 the highest priority interrupt Change the priority of INT1 to the highest priority of all interrupts REVISION HISTORY The first revision of this data sheet (271214-001) indicated only 8 MHz and 13 MHz availability The M80C186EB will also be available in a 16 MHz version The cover and various other locations in the data sheet reflect the additional product speed offering The following list reflects the changes made between the -001 version and this -002 version of the M80C186EB data sheet 1 Operating Conditions section updated to reflect 16 MHz Input clock frequency limits 2 DC Specifications section Added notes regarding untested values added changed input leakage current and input current symbols and values added 16 MHz ICC IID and IPD values 3 AC Specifications section Added full 16 MHz AC Characteristics added note about untested values and reduced minimum output delays (TCHOV and TCLOV) for all speeds 4 Modified Errata section to reflect B-step known errata (INT1 acknowledge anomaly) 1 2 INTEL CORPORATION 2200 Mission College Blvd Santa Clara CA 95052 Tel (408) 765-8080 INTEL CORPORATION (U K ) Ltd Swindon United Kingdom Tel (0793) 696 000 INTEL JAPAN k k Ibaraki-ken Tel 029747-8511 Printed in U S A M379 1296 2K HP DM Military and Special Products |
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